Research

Publications with newest first. A complete list is on my Google Scholar page.

Book chapters

  1. B. K. Joardar, J. R. Doppa, P. P. Pande, “Machine Learning for Heterogeneous Manycore Design,” in Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing, S. Pasricha and M. Shafique (eds), Springer, Cham
  2. Y. Ma, B. K. Joardar, P. P. Pande, A. Joshi, “Interconnect and Integration Technology,” in Emerging Computing: From Devices to Systems. Computer Architecture and Design Methodologies, M. M. S. Aly and A. Chattopadhyay (eds), Springer, Singapore

Journal publications

  1. M. Heidary, B. K. Joardar, “Attacking AI Accelerators via Arithmetic Properties,” in Springer Nature, 2026
  2. A. R. Bommana, F. Firouzi, C. Ogbogu, B. K. Joardar, J. R. Doppa, P. P. Pande, and K. Chakrabarty, “SEC-CiM+: Selective and Reconfigurable Error Compensation for ReRAM-based Compute-in-Memory,” in ACM Transactions on Design Automation of Electronic Systems, Just Accepted (May 2026)
  3. S. S. KC, S. N. Bhat, S. Ravichandran, B. K. Joardar and S. K. Mandal, “InDenT: An Energy-Efficient 2.5D System With Heterogeneous Reconfigurable Interconnect for Dense Foundational Models,” in IEEE Transactions on Circuits and Systems for Artificial Intelligence, vol. 2, no. 4, pp. 315-325, Dec. 2025
  4. G. Narang, C. Ogbogu, B. K. Joardar, J. R. Doppa, K. Chakrabarty, and P. P. Pande, “GINA: Exploiting Graph Neural Network Layer Features for Energy Efficient Inferencing in NVM-based PIM Accelerators,” in ACM Transactions on Embedded Computing Systems, 24, 5s, Article 116 (September 2025)
  5. P. Edara, S. Banerjee, B. K. Joardar, “Localization of Data Compromised by Hardware Attacks in Machine Learning enabled Cyber-Physical Edge Devices,” in ACM Transactions on Cyber-Physical Systems, 9, 3, Article 27 (July 2025)
  6. C. Ogbogu, B. K. Joardar, K. Chakrabarty, J. R. Doppa, and P. P. Pande, “Data Pruning-enabled High Performance and Reliable Graph Neural Network Training on ReRAM-based Processing-in-Memory Accelerators,” in ACM Transactions on Design Automation of Electronic Systems, 29, 5, Article 72, 29 pages, Sept. 2024 Highlight paper
  7. A. Jaiswal, K. C. S. Shahana, S. Ravichandran, K. Adarsh, H. B. Bhat, B. K. Joardar, S. K. Mandal, “HALO: Communication-aware Heterogeneous 2.5D System for Energy-efficient LLM Execution at Edge,” in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 14, no. 3, pp. 425-439, Sept. 2024 Spotlight paper
  8. C.-Y. Chen, B. K. Joardar, J. R. Doppa, P. P. Pande and K. Chakrabarty, “Mitigating Slow-to-Write Errors in Memristor-Mapped Graph Neural Networks Induced by Adversarial Attacks,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 43, no. 8, pp. 2411-2425, Aug. 2024
  9. B. K. Joardar, J. R. Doppa, H. Li, K. Chakrabarty and P. P. Pande, “ReaLPrune: ReRAM Crossbar-Aware Lottery Ticket Pruning for CNNs,” in IEEE Transactions on Emerging Topics in Computing, vol. 11, no. 2, pp. 303-317, 2023
  10. C. Ogbogu, A. I. Arka, L. Pfromm, B. K. Joardar, J. R. Doppa, K. Chakrabarty, and P. P. Pande, “Accelerating Graph Neural Network Training on ReRAM-Based PIM Architectures via Graph and Model Pruning,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 42, no. 8, pp. 2703-2716, Aug. 2023
  11. B. K. Joardar, T. K. Bletsch and K. Chakrabarty, “Machine Learning-Based Rowhammer Mitigation,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 42, no. 5, pp. 1393-1405, May 2023
  12. C. Ogbogu, A. I. Arka, B. K. Joardar, J. R. Doppa, H. Li, K. Chakrabarty, P. P. Pande, “Accelerating Large-Scale Graph Neural Network Training on Crossbar Diet,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 11, pp. 3626-3637, Nov. 2022
  13. B. K. Joardar, A. Deshwal, J. R. Doppa, P. P. Pande and K. Chakrabarty, “High-Throughput Training of Deep CNNs on ReRAM-based Heterogeneous Architectures via Optimized Normalization Layers,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 5, pp. 1537-1549, May 2022
  14. B. K. Joardar, J. R. Doppa, H. Li, K. Chakrabarty and P. P. Pande, “Learning to Train CNNs on Faulty ReRAM-based Manycore Accelerators,” in ACM Transactions on Embedded Computing Systems, 20, 5s, Article 55, Aug. 2021 (as part of ESWEEK 2021)
  15. A. I. Arka, B. K. Joardar, J. R. Doppa, P. P. Pande and K. Chakrabarty, “Performance and Accuracy Trade-offs for Training Graph Neural Networks on ReRAM-based Architectures,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 10, pp. 1743-1756, Oct. 2021
  16. A. I. Arka, B. K. Joardar, R. G. Kim, D. H. Kim, J. R. Doppa and P. P. Pande, “HeM3D: Heterogeneous Manycore Architecture Based on Monolithic 3D Vertical Integration,” in ACM Transactions on Design Automation of Electronic Systems, 26, 2, Article 16, 2021
  17. B. K. Joardar, J. R. Doppa, P. P. Pande, H. Li and K. Chakrabarty, “AccuReD: High Accuracy Training of CNNs on ReRAM/GPU Heterogeneous 3D Architecture,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 40, no. 5, pp. 971-984, 2021
  18. A. Deshwal, N. K. Jayakodi, B. K. Joardar, J. R. Doppa, and P. P. Pande, “MOOS: A Multi-Objective Design Space Exploration and Optimization Framework for NoC Enabled Manycore Systems,” in ACM Transactions on Embedded Computing Systems, 18, 5s, Article 77, 2019
  19. B. K. Joardar, R. G. Kim, J. R. Doppa, P. P. Pande, D. Marculescu and R. Marculescu, “Learning-based Application-Agnostic 3D NoC Design for Heterogeneous Manycore Systems,” in IEEE Transactions on Computers, vol. 68, no. 6, pp. 852-866, 2019

Conference publications

  1. L Wang, S Zhu, BK Joardar, X Fu, “NNHammerGuard: Leveraging DNNs’ Fault Tolerance for Efficient Row Hammer Defense,” International Conference on Computational Science and Computational Intelligence, pp 395–411, vol 2969. Springer, Cham.
  2. P. Edara, B. K. Joardar, Z. T. Tisha, U. Guin, H. U. Rahman and B. Ray, “Security Vulnerabilities of Semiconductor Memories,” 2026 IEEE 44th VLSI Test Symposium (VTS), Napa, CA, USA, 2026, pp. 1-11
  3. P. Edara, S. Duttala, L. Wang, S. K. Mandal and B. K. Joardar, “PROOF: Predetermined Signature-Based On-Chip Online Rowhammer Bit-Flip Detection,” 2025 First International Conference on Intelligent Computing and Systems at the Edge (ICEdge), Bangalore, India, 2025, pp. 1-7
  4. S. S. K. C, S. K. Mandal and B. K. Joardar, “Acceleration of Large Language Models with Emerging Compute and Communication Technology,” 2025 IEEE International Conference on Omni-layer Intelligent Systems (COINS), Madison, WI, USA, 2025, pp. 1-6
  5. M. Heidary, B. K. Joardar, “Aging Attack on Systolic Array-based AI Accelerators via NBTI-Induced Aging,” International Symposium on Quality Electronic Design (ISQED), 2025
  6. M. Heidary and B. K. Joardar, “Hardware Attacks on ReRAM-Based AI Accelerators,” 2024 IEEE 17th Dallas Circuits and Systems Conference (DCAS), TX, USA, 2024, pp. 1-4
  7. P. Dhingra, C. Ogbogu, B. K. Joardar, J. R. Doppa, A. Kalyanaraman and P. P. Pande, “FARe: Fault-Aware GNN Training on ReRAM-Based PIM Accelerators,” 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), Valencia, Spain, 2024, pp. 1-6
  8. C. Ogbogu, M. Soumen, B. K. Joardar, J. R. Doppa, D. Heo, K. Chakrabarty, P. P. Pande, “Energy-Efficient ReRAM-Based ML Training via Mixed Pruning and Reconfigurable ADC,” 2023 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), Vienna, Austria, 2023, pp. 1-6
  9. E. Ortega, T. Bletsch, B. Joardar, J. Talukdar, W. Paik and K. Chakrabarty, “Simply-Track-and-Refresh: Efficient and Scalable Rowhammer Mitigation,” 2023 IEEE International Test Conference (ITC), CA, USA, 2023, pp. 340-349
  10. C. Y. Chen, B. K. Joardar, J. R. Doppa, P. P. Pande and K. Chakrabarty, “Attacking Memristor-Mapped Graph Neural Network by Inducing Slow-to-Write Errors,” 2023 IEEE European Test Symposium (ETS), Venezia, Italy, 2023, pp. 1-4
  11. C. H. Tung, B. K. Joardar, P. P. Pande, J. R. Doppa, H. H. Li and K. Chakrabarty, “Dynamic Task Remapping for Reliable CNN Training on ReRAM Crossbars,” 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), Antwerp, Belgium, 2023, pp. 1-6
  12. B. K. Joardar and K. Chakrabarty, “Attacking ReRAM-based Architectures using Repeated Writes,” 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), Antwerp, Belgium, 2023, pp. 1-6
  13. B. K. Joardar, A. I. Arka, J. R. Doppa, P. P. Pande, “Fault-Tolerant Deep Learning Using Regularization,” 41st International Conference on Computer-Aided Design (ICCAD '22), New York, NY, USA, Article 159, 1-6, 2022
  14. B. K. Joardar, J. R. Doppa, P. P. Pande and K. Chakrabarty, “NoC-enabled 3D Heterogeneous Manycore Systems for Big-Data Applications,” 2022 23rd International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, USA, 2022, pp. 1-6
  15. B. K. Joardar, T. K. Bletsch, and K. Chakrabarty, “Learning to Mitigate Rowhammer Attacks,” Design, Automation & Test in Europe Conference & Exhibition (DATE), 2022, pp. 564-567
  16. B. K. Joardar, J. R. Doppa, P. P. Pande, H. Li and K. Chakrabarty, “Processing-in-Memory enabled Heterogeneous Manycore Architectures for Deep Learning: From CNNs to GNNs,” International Conference on Computer Aided Design (ICCAD), 2021
  17. A. I. Arka, B. K. Joardar, J. R. Doppa, P. P. Pande and K. Chakrabarty, “DARe: DropLayer-Aware Manycore ReRAM Architecture for Training Graph Neural Networks,” International Conference on Computer Aided Design (ICCAD), 2021
  18. X. Yang, S. Belakaria, B. K. Joardar, H. Yang, J. R. Doppa, P. P. Pande, K. Chakrabarty and H. Li, “Multi-Objective Optimization of ReRAM Crossbars for Robust DNN Inferencing under Stochastic Noise,” International Conference on Computer Aided Design (ICCAD), 2021
  19. B. K. Joardar, A. I. Arka, J. R. Doppa and P. P. Pande, “3D++: Unlocking the Next Generation of High-Performance and Energy-Efficient Architectures using M3D Integration,” Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, 2021
  20. A. I. Arka, B. K. Joardar, J. R. Doppa, P. P. Pande and K. Chakrabarty, “ReGraphX: NoC-enabled 3D Heterogeneous ReRAM Architecture for Training Graph Neural Networks,” Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, 2021 Best Paper Nomination
  21. B. K. Joardar, N. K. Jayakodi, J. R. Doppa, H. Li, P. P. Pande and K. Chakrabarty, “GRAMARCH: A GPU-ReRAM based Heterogeneous Architecture for Neural Image Segmentation,” 23rd IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, 2020 Best Paper Nomination
  22. B. K. Joardar, P. Ghosh, P. P. Pande, A. Kalyanaraman and S. Krishnamoorthy, “NoC-enabled Software/Hardware Co-Design Framework for Accelerating k-mer Counting,” International Symposium on Networks-on-Chip (NOCS '19), New York, NY, USA, 2019 Best Paper Award
  23. P. Bogdan, F. Chen, A. Deshwal, J. R. Doppa, B. K. Joardar, H. Li, S. Nazarian, L. Song, and Y. Xiao, “Taming extreme heterogeneity via machine learning based design of autonomous manycore systems,” International Conference on Hardware/Software Codesign and System Synthesis Companion (CODES/ISSS), 2019
  24. B. K. Joardar, A. Deshwal, J. R. Doppa and P. P. Pande, “A Machine Learning Framework for Multi-Objective Design Space Exploration and Optimization of Manycore Systems,” 2019 ACM/IEEE 1st Workshop on Machine Learning for CAD (MLCAD), Canmore, AB, Canada, 2019, pp. 1-6
  25. B. K. Joardar, R. G. Kim, J. R. Doppa, P. P. Pande, “Design and Optimization of Heterogeneous Manycore Systems enabled by Emerging Interconnect Technologies: Promises and Challenges,” 22nd IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition (DATE), Florence, Italy, 2019
  26. B. K. Joardar, B. Li, J. R. Doppa, H. Li, P. P. Pande and K. Chakrabarty, “REGENT: A Heterogeneous ReRAM/GPU-based Architecture Enabled by NoC for Training CNNs,” 22nd IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition (DATE), Florence, Italy, 2019
  27. B. K. Joardar, J. R. Doppa, P. P. Pande, D. Marculescu and R. Marculescu, “Hybrid On-Chip Communication Architectures for Heterogeneous Manycore Systems,” 37th IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2018
  28. B. K. Joardar, K. Duraisamy and P. P. Pande, “High performance collective communication-aware 3D Network-on-Chip architectures,” 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, Germany, 2018, pp. 1351-1356
  29. B. K. Joardar, W. Choi, R. G. Kim, J. R. Doppa, P. P. Pande, D. Marculescu and R. Marculescu, “3D NoC-Enabled Heterogeneous Manycore Architectures for Accelerating CNN Training: Performance and Thermal Trade-offs,” 11th IEEE/ACM International Symposium on Networks-on-Chip (NOCS '17), New York, NY, USA, 2017, Article 18
  30. S. Das, S. Chatterjee, B. K. Joardar, A. Mukherjee, and M. K. Naskar, “Physical channel modeling by calcium signaling in molecular communication based nanonetwork,” 10th EAI International Conference on Body Area Networks (BodyNets '15), Brussels, Belgium, pp. 71-77, 2015