The availability of different core architectures (CPUs, GPUs, NVMs, FPGAs, etc.) and interconnection technologies (e.g., TSV-based stacking, M3D, Photonics, Wireless etc.) has revolutionized high-performance hardware design.
However, the resulting diversity in the choice of hardware has made the design, evaluation, and testing of new architectures an increasingly challenging problem.
Each computation/communication element has its unique set of requirements that need to be satisfied simultaneously for overall power, performance and area benefits.
Existing heuristic-based solutions are not scalable and often lead to sub-optimal outcomes. ML techniques can be used here to solve this problem.
By learning the design space of all possible solutions, ML can lead to better results much faster than traditional methods. This will reduce design time and lead to better architectures in future.
- B. K. Joardar, R. G. Kim, J. R. Doppa, P. P. Pande, D. Marculescu and R. Marculescu, “Learning-based Application-Agnostic 3D NoC Design for Heterogeneous Manycore Systems," in IEEE Transactions on Computers, vol. 68, no. 6, pp. 852-866, 2019
- A. Deshwal, N. K. Jayakodi, B. K. Joardar, J. R. Doppa, and P. P. Pande, “MOOS: A Multi-Objective Design Space Exploration and Optimization Framework for NoC Enabled Manycore Systems,” in ACM Transactions on Embed. Comput. Syst. 18, 5s, Article 77, 2019
- A. I. Arka, B. K. Joardar, R. G. Kim, D. H. Kim, J. R. Doppa and P. P. Pande, "HeM3D: Heterogeneous Manycore Architecture Based on Monolithic 3D Vertical Integration," in ACM Transactions on Des. Autom. Electron. Syst, 26, 2, Article 16, 2021
- B. K. Joardar, A. Deshwal, J. R. Doppa, P. P. Pande and K. Chakrabarty, "High-Throughput Training of Deep CNNs on ReRAM-based Heterogeneous Architectures via Optimized Normalization Layers," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2021